Samsung Electronics developed the world’s first 3D Stacked Field-Effect Transistor (FET). The company presented the innovation at the 2026 VLSI Symposium, where it received the Best Paper award.
This architecture achieves an industry-first gate pitch of 42 nanometers. This specification surpasses the previous industry minimum of 48nm. The design marks a shift from horizontal to vertical transistor structures for logic chips.
Vertical stacking allows Samsung to double the number of transistors within the same surface area. This breakthrough overcomes the physical limitations of traditional 2D scaling. The technology significantly increases computing performance and power efficiency.
Samsung is extending its vertical stacking leadership from V-NAND and HBM memory to the logic chip sector. The 3D Stacked FET will support next-generation processors for artificial intelligence and high-performance computing.